BL7430EC 104-bit eeprom smart counter circuit http://www.belling.com.cn - 1 - 8/16/2006 total 4 pages description BL7430EC is a ic card chip (module)made by 1.2 m mcmos eerpom process. it has 104 bits eeprom with logical encryption and function. it can be widely used in payphone card and other kinds of prepay ic cards. c 1 c 2 c 3 c 7 c 6 c 5 v cc rst clk gnd n.c. i/o pin assignment features 104 x 1 bit organization maximum of 20480 counting units logical encryption eeprom programming time :5ms supply voltage:5v working current:<1ma minimum erasing times 100,000 data retention time :>10 years contacts configuration and serial interface accordi ng to iso 7816 standard (synchronous transmission) pin description pin no. parameter symbol test condition 1 c1 v cc supply voltage 2 c2 rst control input (reset signal) 3 c3 clk clock input 4 c5 gnd ground 5 c6 n.c. not connected 6 c7 i/o bidrectional data line (open drain) function description block diagram
BL7430EC 104-bit eeprom smart counter circuit http://www.belling.com.cn - 2 - 8/16/2006 total 4 pages BL7430EC circuits consists of 104 bits eeprom. the whole storing area is divided into three areas according to different usage. organization of memory pin no. address memory type function 1 0~15 rom manufacturer code 2 16~63 prom card data 64 prom control flag 65~71 prom uppermost non-erasable counter stage; up to 3 bits(69~71) already canedled by testing upon delivery 3 72~103 eeprom count range mentioned above is the user mode after card being personalized. when chips are transferred to card-manufacturer, they are in issue mode, after being personalized, then changed to user mode. the differences between issue mode and user mode are presented on the right figure. counting method the counting area consists of 36 bits eeprom. the s tructure of counter is 5-stage with 8 bits , each stage like an abcus, but the highest stage has only 4 bits, the counting scope is 20480,while counting, the first stage is erased after writing a ny bit of the second counting stage, all do like this, then the fourth counting stage is erased afte r writing any bit of the fifth stage. but the fifth counting stage can be erased, so the contents of co unting cells are continuously reduced to zero. in one counting stage, if the writable numbers more than the number which should be written, this can be operated without any problem. if the writabl e number is less than the number should be written, we can do like this: first write each writ able number of this stage, then we write on bit of higher stage and erase 8 bits of current stage. thu s we can write the remaining number in current stage. reading/writing operation reading operation internal address-counter works following bit clock, at the clock rising edge and rst is low ,the address-counter add 1 after the clock falling edge, the content of the relative address is output to i/o port. both clk and rst are high , the address-c ounter is reset to 0. add a0 a1 a2 do0 do1 io clk rst t r t h t l t r t f t d1 t d2 t d3 t d4 setting address and readout
BL7430EC 104-bit eeprom smart counter circuit http://www.belling.com.cn - 3 - 8/16/2006 total 4 pages writing operation when rst=1 and clk=0, we set r mark, under this con dition if next clock pulse comes the address-counter will not increase and go into writi ng operation during the clock high level. the address-counter is re-effective and writing is fini shed at the clock falling edge. during the issue mode, r mark is useless to the cells of manufacture r code area; during the user mode, r mark is useless to the cells of code area for both manuf acturer and issuer. add n n+1 n+2 io clk rst t d5 n n+1 n+1 t d6 t d7 t s t hw write address erasing operation erasing operation to any stage will lead to the aut omatic erasing of next lower stage. add n n+1 io clk rst t s t hw n n t d6 n t he t s t d7 erasing 8 bits with carry power on and reset the address is reset after power on. rst keep1 an d must last longer than one clock cycle. when rst is changed to low level, the content in th e 0 address is shown on i/o port. the unstability of v cc also can induce the address reset . about comparison of transmission password password comparison must be executed immediately af ter write 0 operation rst clk address i/o d8 1 d8 2 d103 d8 0 d0 0 1 104 81 82 80 103 td8 td9 td10 ec bit addr bit output write one bit ec ec(lsb-1) ~ec(msb-1) thw package module package, the module type according to custom er demand.
BL7430EC 104-bit eeprom smart counter circuit http://www.belling.com.cn - 4 - 8/16/2006 total 4 pages electrical parameter absolute maximum ratings limit values parameter symbol min. typ. max unit test condition supply voltage v cc -0.3 6.0 v input voltage (any pin) v i -0.3 6.0 v storage temperature t s -40 125 esd protection vs 4000 v iso/iec 7816-1 endurance 10 5 write/erase cycles/bit data retention 10 years operation range limit values parameter symbol min. typ. max unit test condition supply voltage v cc 4.75 5.0 5.5 v supply current i cc 3.0 ma v cc =5v ambient temperature ta -35 +80 dc characteristics limit values parameter symbol min. typ. max unit test condition high-level input voltage (i/o,clk,rst) v in 3.5 v cc v low-level input voltage (i/o,clk,rst) v il 0.8 v low-level output current(i/o) i ol 1 ma v ol =0.5v,open drain high-level output current(i/o) i ol 10 m a v oh =0.5v,open drain ac characteristics limit values parameter symbol min. typ. max unit test condition rst(address reset) t r 50 m s rst(set r-flag) t s 10 m s clk (count,h-level) t h 10 m s clk (count,l-level) t l 10 m s clk (write,h-level) t hw 5 ms clk (erase,h-level) t he 5 ms delay time t d1 5 m s t d2 5 m s t d3 5 m s t d4 3.5 m s t d5 5 m s t d6 5 m s t d7 10 m s t d8 3.5 m s t d9 3.5 m s t d10 3.5 m s
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